The present invention relates to the field of integrated circuits, and more particularly to the fields of integrated circuit testing, fault generation, and/or test pattern generation.
Fault modeling techniques are discussed, for example, in U.S. Pat. No. 5,546,408 to Keller entitled xe2x80x9cHierarchical Pattern Faults For Describing Logic Circuit Failure Mechanismsxe2x80x9d, the disclosure of which is incorporated herein in its entirety by reference. In automatic test generation programs, some type of defect model is generally used to identify test stimulus patterns for detecting the modeled defects. The defect model is also used to ascertain the effectiveness of the generated test stimulus patterns in detecting the defects.
Traditionally a xe2x80x9cstuck-atxe2x80x9d fault model has been used in the test industry. That is, a defect is modeled as a node or pin that is shorted to (stuck-at) another node or pin, such as a logic one level or a logic zero level. More recently, a transition fault model has been used to model dynamic defects that require a sequence of two test stimulus patterns to excite the defect.
As discussed in the Keller ""408 patent, a xe2x80x9cpattern faultxe2x80x9d is defined as a static pattern fault or as a dynamic pattern fault. A static pattern fault is represented as a list of required excitation nodes and their values, as well as a fault propagation point. The fault propagation point is defined to be a net or node in a circuit to be tested where the defect""s effect first appears once it has been excited. A dynamic pattern fault adds to this structure an initial value list of nodes and their required initial values. The dynamic pattern fault may be employed when a two pattern sequence is required to excite a specific defect.
Integrated circuit faults can be characterized according to embodiments of the present invention using fault tuples. An integrated circuit device, for example, may include primary inputs, primary outputs, and a plurality of signal lines and circuits interconnecting the primary inputs and outputs. A fault tuple, according to embodiments of the present invention, can be defined to include an identification of a signal line, a signal line value, and a clock cycle constraint for the signal line. The fault tuple is satisfied by providing a test sequence comprising one or more test patterns such that the signal line is controlled to the signal line value during a clock cycle of the test sequence defined by the clock cycle constraint responsive to application of the test sequence to the primary inputs.
Fault tuples, products of fault tuples, and/or macrofaults of OR-ed products of fault tuples can be used to generated test patterns for integrated circuit devices. For example, at least one fault tuple can be provided including an identification of a signal line, a signal line value, and a clock cycle constraint for the signal line. A test sequence comprising at least one test pattern can be determined such that the test sequence can be applied to the primary inputs of the integrated circuit device to control the signal line to the signal line value during a clock cycle of the test sequence defined by the clock cycle constraint.
Fault tuples, products of fault tuples, and/or macrofaults of OR-ed products of fault tuples can also be used to simulate test patterns for faults of an integrated circuit device. For example, a fault tuple can be provided including an identification of a signal line, a signal line value, and a clock cycle constraint for the signal line. A test sequence comprising one or more test patterns can also be provided. Simulation according to embodiments of the present invention can determine if the fault tuple will be satisfied by the test pattern such that the signal line is controlled to the signal line value during a clock cycle of the test sequence defined by the clock cycle constraint responsive to application of the test sequence to the primary inputs.